Electrostatic Discharge (ESD) is a known problem in the manufacturing and the using of integrated circuits. Typically, transistors have thin oxides and insulating layers that can be damaged by the electrostatic discharge, and special care is required to protect the integrated circuits from the damage caused by the ESD.
In high-voltage (HV) applications, ESD protection circuits are also needed. The ESD protection circuits may include ESD power clamps coupled between HV power nodes and electrical grounds. Conventional ESD power clamps may be implemented using Bipolar-Junction Transistors (BJTs), which are electrically broken down by ESD transients to conduct ESD currents. A conventional ESD power clamp may include a High Voltage N-Well (HVNW) region and a High Voltage P-Well (HVPW) region next to, and contacting, each other. A first shallow n-well region and a second shallow n-well region are formed in the HVNW region and HVPW region, respectively. The HVNW region and the HVPW region are further located over an n-type buried layer. A shallow trench isolation region is disposed between the first and the second shallow n-well regions, and extends from the HVNW region to the HVPW region. the ESD power clamp may further include a shallow p-well region may also be formed in the HVPW region. N+ regions and P+ regions. The power clamp forms a bipolar transistor, which is turned on to conduct ESD currents when there is an ESD transient on VDD.